Many communication systems utilize turbo codes to send data from a transmitter to a receiver. The data are coded by the transmitter by means of turbo codes and decoded in iterative fashion at the receiver end. A telecommunications network utilizing the UMTS standard is an example of such a system. Between the transmitter and the receiver the data are passing over a channel. This channel may produce noise which may generate errors in the data received by the receiver.
The use of turbo codes permits a proper error correction at the receiver end. Thus, such a communication system produces a relatively low error rate.
FIG. 1 represents an example of a communication system that utilizes turbo codes. Such a system comprises an encoding device ENC, a transmission channel CHAN and a decoding device DEC. At the level of the encoding device ENC a data vector S1 is coded by a first systematic recursive coder 11 to produce a first parity vector P1. In parallel, the data of the data vector S1 are interleaved by a first interleaver 12 and the vector which is the result thereof is coded by a second systematic recursive coder 13 to produce a second parity vector P2.
The data interleaving of a vector comprises permuting the components of this vector in a predefined order in order to obtain another vector. In the following the interleaving of data of a vector or the interleaving of the vector will be discussed indiscriminately in order to simplify the description.
Then the data vector S1, the first parity vector P1 and the second parity vector P2 are sent over the transmission channel CHAN to the decoding device DEC.
The decoding device DEC comprises a first decoder 14, a second decoder 16, a second interleaver 15, a third interleaver 17 and a de-interleaver 18. In the example of FIG. 1 the decoders 14 and 16 are soft-input-soft-output (SISO) decoders.
This decoding device DEC operates in iterative manner. During an iteration the first decoder 14 calculates a first extrinsic output data vector from the received data vector S1, the first received parity vector P1 and an extrinsic data vector coming from the second decoder 16. If there is not yet an extrinsic data vector coming from the second decoder 16, it is replaced by a predefined vector, for example, a unit vector. This is possible when a decoding is iterated for the first time.
The first extrinsic output data vector is interleaved by means of the second interleaver 15, and the vector resulting therefrom is sent to the second decoder 16. The second decoder 16 then calculates a second extrinsic output data vector from the second parity vector P2, a vector S2 coming from the third interleaver 17 having for its input the data vector S1, and the vector coming from the second interleaver 15. The second extrinsic output data vector is then de-interleaved by the de-interleaver 18 and the resulting vector is sent to the first decoder 14. A new iteration may then be effected.
FIG. 2 represents an example of the architecture permitting to implement the decoding device DEC. The decoding device DEC comprises a decoder 20, a first memory 21 and a second memory 22.
The decoder 20 alternately plays the role of first decoder 14 and second decoder 16. The decoder 20 thus operates in two modes:                a SISO1 mode in which the decoder 20 acts as the first decoder 14 of FIG. 1,        a SISO2 mode in which the decoder 20 acts as the second decoder 16 of the FIG. 1.        
During an iteration the decoder 20 in the SISO1 mode processes input vectors as this has been described in detail in FIG. 1, and calculates a first extrinsic output data vector. The decoder 20 then goes to the SISO2 mode, processes input vectors and calculates a second extrinsic output data vector. The decoder 20 thus needs to read extrinsic data from and write extrinsic data in a memory. The extrinsic data are stored in the first and second memories 21 and 22.
When the decoder 20 is in the SISO1 mode it effects a de-interleaved reading 23 of the extrinsic data vector stored in the second memory 22. It then calculates the first extrinsic output data vector and performs a linearly writing 24 of this first extrinsic output data vector in the first memory 21. Then the decoder 20 changes to the SISO2 mode.
When the decoder 20 is in the SISO2 mode, it carries out an interleaved reading 25 of the extrinsic data vector stored in the first memory 21. It then calculates the second extrinsic output data vector and performs a linearly writing 26 of this second extrinsic output data vector in the second memory 22.
The de-interleaved reading 23 and the interleaved reading 25 are performed by a de-interleaver and an interleaver respectively, not shown in FIG. 2.
A drawback of this decoding system resides in the fact that two memories are necessary for storing the extrinsic data vectors. In the turbo decoders used, for example, in the UMTS standard, an extrinsic data vector contains 5114 bits of data. In consequence, the set of memories necessary for storing the extrinsic data has a considerable size, which is cumbersome because this requires a considerable silicon surface in a circuit accommodating such a turbo decoder.
This set of memories constitutes an extrinsic data memory system.